Storage devices enable users to store and retrieve data. For example, some storage devices include non-volatile memory to store data and a controller that coordinates access to the non-volatile memory and performs error detection/correction. Low-density parity-check (LDPC) is a type of error correction coding (ECC) mechanism that can be performed by a storage device. When bit error rate (BER) is high, the LDPC ECC engine may use a combination of soft bits and hard bits to decode data read from the non-volatile memory. Using the soft bits may improve an error correction capability of the LDPC ECC engine. However, additional sense and data transfer operations used to determine the soft bits may increase overall latency at a storage device. Moreover, when average BER is high, soft bits may be provided and used for an entire page of data, even though the BER for individual data portions (e.g., sub codes) may be low enough to perform successful decoding without the use of soft bits. Additionally, sub codes are usually processed in the same order, regardless of the individual BER, which may contribute to the latency increase.